The fabrication of integrated circuits involves the creation of several layers of materials that interact in some fashion. One or more of these layers may be patterned so various regions of the layer have different electrical characteristics, which may be interconnected within the layer or to other layers to create electrical components and circuits. These regions may be created by selectively introducing or removing various materials. The patterns that define such regions are often created by lithographic processes. For example, a layer of photoresist material is applied onto a layer overlying a wafer substrate. A photomask (containing clear and opaque areas) is used to selectively expose this photoresist material by a form of radiation, such as ultraviolet light, electrons, or x-rays. Either the photoresist material exposed to the radiation, or that not exposed to the radiation, is removed by the application of a developer. An etchant may then be applied to the layer not protected by the remaining resist, and when the resist is removed, the layer overlying the substrate is patterned.
Lithographic processes such as that described above are also typically used to transfer patterns from a photomask to a device. As feature sizes on semiconductor devices decrease into the submicron range, there is a need for new lithographic processes, or techniques, to pattern, for example, high-density semiconductor devices. Several new lithographic techniques which accomplish this need and have a basis in imprinting and stamping have been proposed. One in particular, Step and Flash Imprint Lithography has been shown to be capable of patterning lines as small as 20 nm.
Step and Flash Imprint Lithography templates are typically made by applying a layer of chrome, 2–100 nm thick, on to a transparent quartz plate. A resist layer is applied to the chrome and patterned using either an electron beam or optical exposure system. The resist is then placed in a developer to form patterns on the chrome layer. The resist is used as a mask to etch the chrome layer. The chrome then serves as a hard mask for the etching of the quartz plate. Finally, the chrome is removed, thereby forming a quartz template containing relief images in the quartz.
Overall, Step and Flash Imprint Lithography techniques benefit from their unique use of photochemistry, the use of ambient temperatures, and the low pressure required to carry out the Step and Flash Imprint Lithography process. During a typical Step and Flash Imprint Lithography process, a substrate is coated with an organic planarization layer (also known as a transfer layer), and brought into close proximity of a transparent Step and Flash Imprint Lithography template, typically comprised of quartz, containing a relief image and coated with a low surface energy material. An ultraviolet or deep ultraviolet sensitive photocurable organic solution is deposited between the template and the coated substrate. Using minimal pressure, the template is brought into contact with the substrate, and more particularly the photocurable organic layer (also known as an etch barrier). Next, the organic layer is cured, or crosslinked, at room temperature by illuminating through the template. The light source typically uses ultraviolet radiation. A range of wavelengths (150 nm–500 nm) is possible, depending upon the transmissive properties of the template and photosensitivity of the photocurable organic layer. The template is next separated from the substrate and the organic layer, leaving behind an organic replica of the template relief on the planarization layer. This pattern is then etched with a short halogen break-through, followed by either an oxygen or ammonia dry etch process, for example, RIE (reactive ion etch), ICP (inductively coupled plasma), ECR (electron cyclotron resonance), to form a high-resolution, high aspect-ratio feature in the organic layer and planarization layer. Thus, the current state-of-the-art requires two etch steps for feature pattern transfer.
Step and Flash Imprint Lithography technology has been demonstrated to resolve features as small as 20 nm. As such, a wide variety of feature sizes may be drawn on a single wafer. Certain problems exist though with this Step and Flash Imprint Lithography pattern transfer methodology as described above. In particular, a potential exists for critical dimension bias and added defects due to the planarization layer etch. Further, it would be advantageous to develop a process without the planarization layer because that would require one less processing step, thereby reducing cost of any devices fabricated in this way. Oxygen and ammonia are typically used to obtain good etch selectivity between the etch barrier and the planarization layer when the silicon content of the etch barrier is low, for example, equal to or below 10%. Poor selectivity results in feature size or critical dimension bias.